An area-efficient and wide-range digital DLL for per-pin deskew applications

In this work, we present a 200 MHz to 1.6 GHz digital delay-locked loop (DLL) for per-pin deskew applications. The proposed phase shifters apply linear and scalable circuit architecture for the pin-to-pin delay mismatch of parallel I/O pins. The proposed phase detector with a detection window and the proposed consecutive phase decision method reduce the sensitivity to reference clock jitter. A test chip of the 0.042 mm DLL and the 3-ps-adjustable-resolution phase shifters with a 0.0025 mm per-channel area was implemented using a 90-nm CMOS process. Simulation results show that the phase error of the 90◦ phase shifter at 1.6 GHz is 2.4◦ . The DLL and the phase shifter consume 3.4 mW and 0.31 mW, respectively, at 1.6 GHz.